This invention relates to means for testing a "long" counter, (i.e., one having many stages) where the inputs and outputs of each stage of the counter are not accessible.
By way of example, a large complex system including a digital frequency synthesizer formed on an integrated circuit (IC) may include one or more "long" counter circuits "embedded" on the same IC. The "long" counters are characterized as being "embedded" in that due to the complexity of the system and the limited number of pin connections that can be made to the IC, it is not desirable and/or possible to access the inputs and outputs of individual counter stages. For example, refer to FIG. 1 which shows a simplified block diagram of a typical phase locked loop digital frequency synthesizer suitable for use in a cordless or cellular telephone. The synthesizer includes an input terminal, 101, to which is applied a first input signal, fin. The signal fin is applied to an M-bit reference divider 102. In this example, M is equal to 12 and divider 102 is a 12 bit binary counter/divider. A reference output signal (fr) produced at the output of divider 102 is fed to an input of a phase comparator 103. Another input of comparator 103 is connected to the output (ff) of an N-bit programmable main divider/counter 104. In this example, N is 24 bits and counter 104 may be set to divide or count up to a maximum of 24 bits (i.e.,2.sup.24). The outputs (u,d) of the phase comparator 103 are applied to the inputs of a charge pump 105 whose output is applied to the input of a low pass filter 106 whose output is fed to the input of a voltage controlled oscillator (VCO) 107 at whose output 108 is produced an output frequency signal fo which is applied to the input of divider 104. The output frequency fo is equal to fin[N/M], where the ratio of N and M may be varied to provide a desired fo. The dividers/counters in the system are critical to its proper operation and to meet requirements of the Federal Communication Commission (FCC). It is therefore necessary to test their operability. However, the frequency synthesizer is part of a complex system and when formed on an IC most of the pins of the IC are required to access more critical system functions. Consequently, a problem exists regarding the testing of the counters/dividers to determine their operability.
The task is rendered more difficult where it is also desirable and/or necessary to test the counters quickly with a minimum amount of additional circuitry. Thus, a problem exists where a long counter has to be tested and the inputs and outputs of the counter stages are not accessible.
A prior art scheme for testing a binary counter is disclosed in U.S. Pat. No. 4,336,448 titled Binary Counter and Circuit For Testing Same to Shipp et al. The '448 patent suggests the partitioning of a ripple counter and then operating the partitioned sections sequentially in order to speed up the time to test the operability of the counter. However, the disclosed scheme is defective in that it only tests whether each section can reach an overflow condition and whether the counter sections overflow. Thus, if a fault exists at some internal point of the sections, the fault will not be detected where an overflow condition is eventually produced. Consequently the prior art scheme does not have extensive fault coverage. Also, in the '448 patent, the tester must wait the full period required for an overflow to occur to ascertain whether there is an error in the counters. Still further in the '448 patent, the counters make use of ripple down binary counters which are prone to noise and which are not synchronous. Consequently, in these type of circuits delays accumulate from stage to stage rendering the scheme inappropriate for high frequency applications. Furthermore, in the '448 patent the clock signal is routed to different sections of the counter via routing logic having different delays. This gives rise to race conditions which limit the speed of operation of the system.
An object of the invention is to provide built-in test circuitry for simplifying and speeding-up the testing of "long" counters while providing extensive fault coverage.